In recent years, as semiconductor integrated circuits (LSIs) used in electronic equipment have become higher in density and degree of integration, the electrode terminals of LSI chips have rapidly become higher in pin count and narrower in pitch. To mount such an LSI chip on a circuit board, flip chip mounting has been used widely for a reduction in wiring delay. In the flip chip mounting, it is typical to form solder bumps on the electrode terminals of an LSI chip and simultaneously bond the electrode terminals to connecting terminals formed on a circuit board via the solder bumps.
To mount a next-generation LSI having electrode terminals the number of which is over 5,000, it is needed to form bumps corresponding to a narrower pitch of not more than 100 μm. However, with a current solder-bump forming technology, it is difficult to respond to the need. In addition, it is needed to form a large number of bumps corresponding to the number of electrode terminals. Therefore, to reduce cost, it is also required to achieve high productivity by reducing a mounting tact time per chip.
Likewise, due to an increased number of electrode terminals, the semiconductor integrated circuit has shifted from the use of peripheral electrode terminals to that of area array electrode terminals. Under the higher-density and higher- integration requirements, it is expected that the scale of a semiconductor process advances from 90 nm to 65 nm and 45 nm. As a result, the miniaturization of wiring further proceeds and a wire-to-wire capacitance increases so that problems associated with a higher speed and a power consumption loss have become serious and demand for a low-dielectric-constant (low-k) insulating film between wiring layers has further grown. Such a low-k insulating film can be implemented by porosifying an insulating layer material so that the mechanical strength thereof is low, presenting an obstacle to a reduction in the thickness of a semiconductor. Moreover, when area array electrode terminals are constructed as described above, there is a problem in the strength of a low-k porous film. Consequently, it has become difficult to form bumps on the area array electrodes and perform flip chip mounting itself. As a result, there has been demand for a low-load flip chip mounting method suitable for a higher-density thin semiconductor compatible with the future advancement of a semiconductor process.
As conventional bump forming techniques, a plating method, a screen printing method, and the like have been developed. The plating method is suitable for a narrow pitch, but has a problem in productivity because of complicated process steps. The screen printing method is excellent in productivity, but is not suitable for a narrow pitch because of the use of a mask.
In such a situation, several techniques which selectively form solder bumps on the electrodes of an LSI chip and a circuit board have been developed recently. These techniques are not only suitable for the formation of micro-bumps but also capable of simultaneously forming the bumps so that they are also excellent in productivity and draw attention as techniques applicable to the mounting of a next-generation LSI on a circuit board.
For example, the technique disclosed in Patent Document 1, Patent Document 2, or the like solidly coats a solder paste composed of a mixture of a solder powder and a flux on a substrate having electrodes formed on the surface thereof, melts the solder powder by heating the substrate, and selectively forms solder bumps on the electrodes having high wettability.
The technique disclosed in Patent Document 3 solidly coats a paste-like composition (deposition-type solder using a chemical reaction) containing an organic acid lead salt and metallic tin as main components on a substrate on which electrodes are formed, causes a substitution reaction between Pb and Sn by heating the substrate, and selectively deposits a Pb/Sn alloy on the electrodes of the substrate.
However, each of the techniques disclosed in Patent Documents 1 to 3 shown above supplies a paste-like composition onto the substrate by coating, local variations in thickness and concentration occur. Accordingly, the amount of a deposited solder differs from one electrode to another and bumps having uniform heights cannot be obtained. In addition, since each of the methods supplies the paste-like composition by coating onto the circuit board having projections and depressions formed in the surface thereof, a sufficient amount of the solder cannot be supplied onto the electrodes forming projecting portions so that it is difficult to obtain bumps of desired heights, which is necessary in flip chip mounting.
In flip chip mounting using a conventional bump forming technique, after a semiconductor chip is mounted on a circuit board on which bumps are formed, the step of injecting a resin termed an underfill into the space between the semiconductor chip and the circuit board is further needed to fix the semiconductor chip to the circuit board.
As a method for simultaneously performing the provision of electrical connection between the facing electrode terminals of the semiconductor chip and the circuit board and the fixation of the semiconductor chip to the circuit board, a flip chip mounting technique (see, e.g., Patent Document 4) using an anisotropic conductive material has been developed. The technique supplies a thermosetting resin containing conductive particles into the space between the circuit board and the semiconductor chip and heats the thermosetting resin, while simultaneously pressing the semiconductor chip, thereby simultaneously implementing the electrical connection between the respective electrode terminals of the semiconductor chip and the circuit board and the fixation of the semiconductor chip to the circuit board.    Patent Document 1: Japanese Laid-Open Patent Publication No. 2000-94179    Patent Document 2: Japanese Laid-Open Patent Publication No. HEI 6-125169    Patent Document 3: Japanese Laid-Open Patent Publication No. HEI 1-157796    Patent Document 4: Japanese Laid-Open Patent Publication No. 2000-332055    Patent Document 5: Japanese Laid-Open Patent Publication No. 2002-26070    Patent Document 6: Japanese Laid-Open Patent Publication No. HEI 11-186334    Patent Document 7: Japanese Laid-Open Patent Publication No. 2004-260131    Non-Patent Document 1: Masahito Yasuda et al., “Self-Organized Joining Assembly Process by Electrically Conductive Adhesive Using Low Melting Point Filler” 10th Symposium on “Microjoining and Assembly Technology in Electronics, pp. 183 to 188, 2004)